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FEATURES Eight 8-Bit DACs with Output Amplifiers Operates with Single +5 V, +12 V or +15 V or Dual Supplies P Compatible (95 ns WR Pulse) No User Trims Required Skinny 24-Pin DlPs, SOIC, and 28-Terminal Surface Mount Packages
LC2MOS Octal 8-Bit DAC AD7228A
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7228A contains eight 8-bit voltage-mode digital-toanalog converters, with output buffer amplifiers and interface logic on a single monolithic chip. No external trims are required to achieve full specified performance for the part. Separate on-chip latches are provided for each of the eight D/A converters. Data is transferred into the data latches through a common 8-bit TTL/CMOS (5 V) compatible input port. Address inputs A0, A1 and A2 determine which latch is loaded when WR goes low. The control logic is speed compatible with most 8-bit microprocessors. Specified performance is guaranteed for input reference voltages from +2 to +10 V when using dual supplies. The part is also specified for single supply +15 V operation using a reference of +10 V and single supply +5 V operation using a reference of +1.23 V. Each output buffer amplifier is capable of developing +10 V across a 2 k load. The AD7228A is fabricated on an all ion-implanted, highspeed, Linear Compatible CMOS (LC2MOS) process which has been specifically developed to integrate high-speed digital logic circuits and precision analog circuits on the same chip.
PRODUCT HIGHLIGHTS
1. Eight DACs and Amplifiers in Small Package The single-chip design of eight 8-bit DACs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all analog inputs and outputs at one side of the package and all digital inputs at the other. 2. Single or Dual Supply Operation The voltage-mode configuration of the DACs allows single supply operation of the AD7228A. The part can also be operated with dual supplies giving enhanced performance for some parameters. 3. Microprocessor Compatibility The AD7228A has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level triggered and speed compatible with most high performance 8-bit microprocessors.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7228A-SPECIFICATIONS
DUAL SUPPLY
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error 3 Relative Accuracy Differential Nonlinearity Full-Scale Error4 Zero Code Error @ 25C TMIN to TMAX Minimum Load Resistance REFERENCE INPUT Voltage Range 1 Input Resistance Input Capacitance 5 AC Feedthrough DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Leakage Current Input Capacitance 5 Input Coding DYNAMIC PERFORMANCE 5 Voltage Output Slew Rate Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough Digital Crosstalk 6 POWER SUPPLIES VDD Range VSS Range IDD @ 25C TMIN to TMAX ISS @ 25C TMIN to TMAX
(VDD = 10.8 V to 16.5 V; VSS = -5 V 10%; GND = 0 V; VREF = +2 V to +10 V1; RL = 2 k, CL = 100 pF unless otherwise noted.) All specifications TMIN to TMAX unless otherwise noted.
B Version2 8 2 1 1 1 25 30 2 2 to 10 2 500 -70 2.4 0.8 1 8 Binary 2 5 5 50 50 10.8/16.5 -4.5/-5.5 16 20 14 18 C Version 8 1 1/2 1 1/2 15 20 2 2 to 10 2 500 -70 2.4 0.8 1 8 Binary 2 5 5 50 50 10.8/16.5 -4.5/-5.5 16 20 14 18 T Version 8 2 1 1 1 25 30 2 2 to 10 2 500 -70 2.4 0.8 1 8 Binary 2 5 5 50 50 10.8/16.5 -4.5/-5.5 16 22 14 20 U Version 8 1 1/2 1 1/2 15 20 2 2 to 10 2 500 -7 0 2.4 0.8 1 8 Binary 2 5 5 50 50 10.8/16.5 -4.5/-5.5 16 22 14 20 Units Bits LSB max LSB max LSB max LSB max mV max mV max k min V min/V max k min pF max dB typ V min V max A max pF max Conditions/Comments
VDD = +15 V 10%, V REF = +10 V Guaranteed Monotonic Typical tempco is 5 ppm/C with VREF = +10 V Typical tempco is 30 V/C VOUT = +10 V
Occurs when each DAC is loaded with all 1s. VREF = 8 V p-p Sine Wave @ 10 kHz
VIN = 0 V or VDD
V/s min s max s max nV secs typ nV secs typ V min/V max V min/V max mA max mA max Outputs Unloaded; V IN = VINL or VINH mA max mA max VREF = +10 V; Settling Time to 1/2 LSB VREF = +10 V; Settling Time to 1/2 LSB Code transition all 0s to all 1s. V REF = 0 V; WR = VDD Code transition all 0s to all 1s. V REF = +10 V; WR = 0 V For Specified Performance For Specified Performance Outputs Unloaded; V IN = VINL or VINH
SINGLE SUPPLY
STATIC PERFORMANCE Resolution Total Unadjusted Error 3 Differential Nonlinearity Minimum Load Resistance REFERENCE INPUT Input Resistance Input Capacitance 5 DIGITAL INPUTS
(VDD = +15 V 10%, VSS; = GND = 0 V; VREF = +10 V, RL = 2 k, CL = 100 pF unless otherwise noted.) AII specifications TMIN to TMAX unless otherwise noted.
8 2 1 2 2 500 8 1 1 2 2 500 8 2 1 2 2 500 8 1 1 2 2 500 Bits LSB max LSB max k min k min pF max
Guaranteed Monotonic VOUT = +10 V
Occurs when each DAC is loaded with all 1s.
As per Dual Supply Specifications 2 5 7 50 50 13.5/16.5 16 20 2 5 7 50 50 13.5/16.5 16 20 2 5 7 50 50 13.5/16.5 16 22 2 5 7 50 50 13.5/16.5 16 22
5 6
DYNAMIC PERFORMANCE 5 Voltage Output Slew Rate Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough Digital Crosstalk 6 POWER SUPPLIES VDD Range IDD @ 25C TMIN to TMAX
V/s min s max s max nV secs typ nV secs typ V min/V max mA max mA max Settling Time to 1/2 LSB Settling Time to 1/2 LSB Code transition all 0s to all 1s. V REF = 0 V; WR = VDD Code transition all 0s to all 1s. V REF = +10 V, WR = 0 V For Specified Performance Outputs Unloaded; V IN = VINL or VINH
NOTES 1 VOUT must be less than VDD by 3.5 V to ensure correct operation. 2 Temperature ranges are as follows: B, C Versions; -40C to +85C T, U Versions; -55C to +125C 3 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 4 Calculated after zero code error has been adjusted out.
Sample tested at 25C to ensure compliance. The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.
Specifications subject to change without notice.
-2-
REV. A
AD7228A +5 V SUPPLY OPERATION unless otherwise noted.) AII specifications T
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error Zero Code Error @ 25C TMIN to TMAX REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Input Capacitance POWER REQUIREMENTS Positive Supply Range Positive Supply Current @ 25C TMIN to TMAX Negative Supply Current @ 25C TMIN to TMAX B Version 8 2 1 4 30 40 1.2 1.3 2 500 4.75/5.25 16 20 14 18 C Version 8 2 1 2 20 30 1.2 1.3 2 500 4.75/5.25 16 20 14 18 T Version 8 2 1 4 30 40 1.2 1.3 2 500 4.75/5.25 16 22 14 20
(VDD = +5 V
5%, VSS; = 0 to -5 V
10%, GND = 0 V, VREF = +1.25 V, RL = 2 k , CL = 100 pF MIN to TMAX unless otherwise noted.
U Version 8 2 1 2 20 30 1.2 1.3 2 500 4.75/5.25 16 22 14 20 Units Bits LSB max LSB max LSB max mV max mV max V min V max k min pF max V min/V max A max A max A max A max For Specified Performance Conditions/Comments
Guaranteed Monotonic
NOTES All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when VSS = 0 V. Specifications subject to change without notice.
SWITCHING CHARACTERISTICS1, 2
Parameters t1 t2 t3 t4 t5 Limit at 25C All Grades 0 0 70 10 95
(See Figures 1, 2; VDD = +5 V
5% or +10.8 V to +16.5 V; VSS = 0 V or -5 V
Units ns min ns min ns min ns min ns min Conditions/Comments
10%)
Limit at TMIN, TMAX (B, C Versions) 0 0 90 10 120
Limit at TMIN, TMAX (T, U Versions) 0 0 100 10 150
Address to WR Setup Time Address to WR Hold Time Data Valid to WR Setup Time Data Valid to WR Hold Time Write Pulse Width
NOTES 1 Sample tested at 25C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, tR = tF = 5 ns.
2
Timing measurement reference level is
V INH + V INL 2
INTERFACE LOGIC INFORMATION
Address lines A0, A1 and A2 select which DAC accepts data from the input port. Table I shows the selection table for the eight DACs with Figure 1 showing the input control logic. When the WR signal is low, the input latch of the selected DAC is transparent, and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value corresponding to the data held in their respective latches.
Table I. AD7228A Truth Table
AD7228A Control Inputs WR A2 A1 H L X L L L L L H H H H X L L L H H L L H H A0 X L L H L H L H L H AD7228A Operation No Operation Device Not Selected DAC 1 Transparent DAC 1 Latched DAC 2 Transparent DAC 3 Transparent DAC 4 Transparent DAC 5 Transparent DAC 6 Transparent DAC 7 Transparent DAC 8 Transparent
Figure 1. Input Control Logic
g
L L L L L L L
H = High State L = Low State X = Don't Care
Figure 2. Write Cycle Timing Diagram
REV. A
-3-
AD7228A
ABSOLUTE MAXIMUM RATINGS 1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +24 V Digital Input Voltage to GND . . . . . . . . . . . . . . . -0.3 V, VDD VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, VDD VOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Power Dissipation (Any Package) to +75C . . . . . . . 1000 mW Derates above 75C by . . . . . . . . . . . . . . . . . . . . 2.0 mW/C Operating Temperature Commercial . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Extended . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Outputs may be shorted to any voltage in the range V SS to VDD provided that the power dissipation of the package is not exceeded. Typical short circuit current for a short to GND or V SS is 50 mA.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7228A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS DIP AND SOIC PLCC CIRCUIT INFORMATION D/A SECTION
WARNING!
ESD SENSITIVE DEVICE
The AD7228A contains eight identical, 8-bit, voltage-mode digital-to-analog converters. The output voltages from the converters have the same polarity as the reference voltage, allowing single supply operation. A novel DAC switch pair arrangement on the AD7228A allows a reference voltage range from +2 V to +10 V when operated from a VDD of +15 V. Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high-speed NMOS switches. The simplified circuit diagram for one channel is shown in Figure 3. Note that VREF and GND are common to all eight DACs.
ORDERING GUIDE
Model1 AD7228ABN AD7228ACN AD7228ABP AD7228ACP AD7228ABR AD7228ACR AD7228ABQ AD7228ACQ AD7228ATQ3 AD7228AUQ3
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C
Total Unadjusted Error (LSB) 2 max 1 max 2 max 1 max 2 max 1 max 2 max 1 max 2 max 1 max
Package Option2 N-24 N-24 P-28A P-28A R-24 R-24 Q-24 Q-24 Q-24 Q-24
Figure 3. D/A Simplified Circuit Diagram
NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local sales office for military data sheet and availability. 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC (SOIC). 3 These grades will be available to /883B processing only.
The input impedance at the VREF pin of the AD7228A is the parallel combination of the eight individual DAC reference input impedances. It is code dependent and can vary from 2 k to infinity. The lowest input impedance occurs when all eight DACs are loaded with digital code 01010101. Therefore, it is important that the external reference source presents a low output impedance to the VREF terminal of the AD7228A under changing load conditions. Due to transient currents at the reference input during digital code changes a 0.1 F (or greater) decoupling capacitor is recommended on the VREF input for dc applications. The nodal capacitance at the reference terminal is also code dependent and typically varies from 120 pF to 350 pF. Each VOUT pin can be considered as a digitally programmable voltage source with an output voltage: VOUTN = DN * VREF where DN is a fractional representation of the digital input code and can vary from 0 to 255/256. The output impedance is that of the output buffer amplifier as described in the following section. -4- REV. A
AD7228A
OP AMP SECTION SUPPLY CURRENT
Each voltage-mode D/A converter output is buffered by a unity gain noninverting CMOS amplifier. This buffer amplifier is tested with a 2 k and 100 pF load but will typically drive a 2 k and 500 pF load. The AD7228A can be operated single or dual supply. Operating the part from single or dual supplies has no effect on the positivegoing settling time. However, the negative-going settling time to voltages near 0 V in single supply will be slightly longer than the settling time for dual supply operation. Additionally, to ensure that the output voltage can go to 0 V in single supply, a transistor on the output acts as a passive pull-down as the output voltage nears 0 V. As a result, the sink capability of the amplifier is reduced as the output voltage nears 0 V in single supply. In dual supply operation, the full sink capability of 400 A at 25C is maintained over the entire output voltage range. The single supply output sink capability is shown in Figure 4. The negative VSS also gives improved output amplifier performance allowing an extended input reference voltage range and giving improved slew rate at the output.
The AD7228A has a maximum IDD specification of 22 mA and a maximum ISS of 20 mA over the -55C to +125C temperature range. This maximum current specification is actually determined by the current at -55C. Figure 6 shows a typical plot of power supply current versus temperature.
Figure 6. Power Supply Current vs. Temperature
APPLYING THIS AD7228A UNIPOLAR OUTPUT OPERATION
Figure 4. Single Supply Sink Current
The output broadband noise from the amplifier is 300 V peak-to-peak. Figure 5 shows a plot of noise spectral density versus frequency.
This is the basic mode of operation for each channel of the AD7228A, with the output voltage having the same positive polarity as VREF. Connections for unipolar output operation are shown in Figure 7. The AD7228A can be operated from single or dual supplies as outlined earlier. The voltage at the reference input must never be negative with respect to GND. Failure to observe this precaution may cause parasitic transistor action and possible device destruction. The code table for unipolar output operation is shown in Table II.
Figure 5. Noise Spectral Density vs. Frequency
DIGITAL INPUTS
The AD7228A digital inputs are compatible with either TTL or 5 V CMOS levels. All logic inputs are static-protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by on-chip distributed diodes. REV. A -5-
Figure 7. Unipolar Output Circuit
AD7228A
Table II. Unipolar Code Table DAC Latch Contents MSB LSB 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 Analog Output
255 +V REF 256 129 +V REF 256 V 128 +V REF = + REF 256 2 127 +V REF 256 1 +V REF 256
Mismatch between R1 and R2 causes gain and offset errors, and therefore, these resistors must match and track over temperature. Once again, the AD7228A can be operated from single supply or from dual supplies. Table III shows the digital code versus output voltage relationship for the circuit of Figure 8 with R1 = R2.
AC REFERENCE SIGNAL
0V
1 256
Note: 1 LSB = (VREF)(2-8) = VREF
In some applications it may be desirable to have an ac signal applied as the reference input to the AD7228A. The AD7228A has multiplying capability within the upper (+10 V) and lower (+2 V) limits of reference voltage when operated with dual supplies. Therefore, ac signals need to be ac coupled and biased up before being applied to the reference input. Figure 9 shows a sine-wave signal applied to the reference input of the AD7228A. For input frequencies up to 50 kHz, the output distortion typically remains less than 0.1%. The typical 3 dB bandwidth for small signal inputs is 800 kHz.
BIPOLAR OUTPUT OPERATION
Each of the DACs on the AD7228A can be individually configured for bipolar output operation. This is possible using one external amplifier and two resistors per channel. Figure 8 shows a circuit used to implement offset binary coding (bipolar operation) with DAC1 of the AD7228A. In this case
R2 R2 V OUT = 1 + * ( D1 *V REF ) - * (V REF ) R1 R1
With R1 = R2 VOUT = (2D1 - 1) * (VREF) where D1 is a fractional representation of the digital word in latch 1 of the AD7228A. (0 D1 255/256)
Figure 9. Applying a AC Signal to the AD7228A
TIMING DESKEW
A common problem in ATE applications is the slowing or "rounding-off" of signal edges by the time they reach the pin-driver circuitry. This problem can easily be overcome by "squaring-up" the edge at the pin-driver. However, since each edge will not have been "rounded-off" by the same extent, this "squaring-up" could lead to incorrect timing relationship between signals. This effect is shown in Figure 10a.
Figure 8. Bipolar Output Circuit
Table III. Bipolar Code Table DAC Latch Contents MSB LSB 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 Analog Output
127 +V REF 128 1 +V REF 128
Figure 10a. Time Skewing Due to Slowing of Edges
0V
1 -V REF 128 127 -V REF 128 128 -V REF = -V REF 128
The circuit of Figure 10b shows how two DACs of the AD7228A can help in overcoming this problem. The same two signals are applied to this circuit as were applied in Figure 10b. The output of each DAC is applied to one input of a high-speed comparator, and the signals are applied to the other inputs. Varying the output voltage of the DAC effectively varies the trigger point at which the comparator flips. Thus the timing relationship between the two signals can be programmably corrected (or deskewed) by varying the code to the DAC of the AD7228A. In a typical application, the code is loaded to the -6- REV. A
AD7228A
DACs for correct timing relationships during the calibration cycle of the instrument.
Figure 12. Self-Programmable Reference
Figure 10b. AD7228A Timing Deskew Circuit
COARSE/FINE ADJUST
The DACs on the AD7228A can be paired together to form a coarse/fine adjust function as indicated in Figure 11. The function is achieved using one external op amp and a few resistors per pair of DACs. DAC1 is the most significant or coarse DAC. Data is first loaded to this DAC to coarsely set the output voltage. DAC2 is then used to fine tune this output voltage. Varying the ratio of R1 to R2 varies the relative effect of the coarse and fine DACs on the output voltage. For the resistor values shown, DAC2 has a resolution of 150 V in a 10 V output range. Since each DAC on the AD7228A is guaranteed monotonic, the coarse adjustment and fine adjustment are each monotonic. One application for this is as a set-point controller (see "Circuit Applications of the AD7226 Quad CMOS DAC" available from Analog Devices, Publication Number E873-15-11/84).
Figure 13. Variation of VREF with Feedback Configuration
MICROPROCESSOR INTERFACING
Figure 14. AD7228A to 8085A/Z80 Interface Figure 11. Coarse/Fine Adjust Circuit
SELF-PROGRAMMABLE REFERENCE
The circuit of Figure 12 shows how one DAC of the AD7228, in this case DAC1, may be used in a feedback configuration to provide a programmable reference for itself and the other seven converters. The relationship of VREF to VIN is expressed by
V REF =
(1 + G * D1)
(1 + G )
*V IN
where G = R2/R1
Figure 13 shows typical plots of VREF versus digital code, D1, for three different values of G. With VIN = 2.5 V and G = 3 the voltage at the output varies between 2.5 V and 10 V giving an effective 10-bit dynamic range to the other seven converters. For correct operation of the circuit, VSS should be -5 V and R1 greater than 6.8 k. REV. A -7-
Figure 15. AD7228A to 6809/6502 Interface
AD7228A
Figure 16. AD7228A to 68008 Interface
Figure 17. AD7228A to MCS-51 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-24)
Cerdip (Q-24)
SOIC (R-24)
PLCC (P-28A)
-8-
REV. A
PRINTED IN U.S.A.
C1663-24-5/92
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